Explorando a Assimetria do Dimensionamento de Transistores CMOS em Portas Complexas
DOI:
https://doi.org/10.5902/2448190485304Keywords:
sizingAbstract
To efficiently design logic gates, it is crucial to size the transistors appropriately to optimize area, propagation delay, and power consumption. There are widely used techniques in the literature for transistor sizing, but it is believed that an alternative sizing approach may offer better results for complex gates. In this context, this study explored asymmetric transistor sizing in complex gates, resulting in improvements in propagation delay for logic gates with large output loads.
Downloads
References
Böhlke, M. S. (2021). Adaptação ao logical effort: Mantendo a simplicidade e reduzindo o consumo em portas complexas. Trabalho de Conclusão de Curso. Universidade Federal de Pelotas.
Callegaro, V., Marques, F. d. S., Klock, C. E., da Rosa Jr, L. S., Ribas, R. P., and Reis, A. I. (2010). Switchcraft: a framework for transistor network design. In Proceedings of the 23rd symposium on Integrated circuits and system design, pages 49–53.
Kessler, H., Böhlke, M., da Rosa, L. S., Porto, M., and Camargo, V. V. (2022a). Calibration of logical effort transistor sizing for on-the-fly low-power supergate design. In 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), pages 1–4. IEEE.
Kessler, H., Porto, M., Da Rosa, L., and Camargo, V. V. (2022b). Standard cell and supergates designs: An electrical comparison on 4-input logic functions. In 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1744–1748. IEEE.
Kessler, H. C. (2022). Static cmos complex gates: electrical investigation of design strategies. Master’s thesis, Universidade Federal de Pelotas.
Kofuji, S. T., Zuffo, J. A., and Soares, J. N. (1990). Circuitos integrados cmos. Disciplina de Eletrônica Experimental.
Marques, F. S., Rosa Jr, L., Ribas, R. P., Sapatnekar, S. S., and Reis, A. I. (2007). Dag based library-free technology mapping. In Proceedings of the 17th ACM Great Lakes symposium on VLSI, pages 293–298.
Moore, G. (1965). Moore’s law. Electronics Magazine, 38(8):114.
Ricci, A., De Munari, I., and Ciampolini, P. (2007). An evolutionary approach for standard-cell library reduction. In Proceedings of the 17th ACM Great Lakes symposium on VLSI, pages 305–310.
Sutherland, I., Sproull, R. F., and Harris, D. (1999). Logical effort: designing fast CMOS circuits. Morgan Kaufmann.
Tseng, I., Postula, A., and Jozwiak, L. (2005). Symbolic extraction for estimating analog layout parasitics in layout-aware synthesis.
Weste, N. and Harris, D. (2011). CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Education.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2023 Revista ComInG - Communications and Innovations Gazette
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
Os manuscritos aceitos e publicados são de propriedade da revista ComInG.
Os originais deverão ser acompanhados de documentos de transferência de direitos autorais contendo assinatura dos autores.
A carta de direitos autorais deve ser enviada para o e-mail coming@inf.ufsm.br
É vedada a submissão integral ou parcial do manuscrito a qualquer outro periódico. A responsabilidade do conteúdo dos artigos é exclusiva dos autores.
É vedada a tradução para outro idioma sem a autorização escrita do Editor ouvida a Comissão Editorial.
ENGLISH
Manuscripts accepted and published are the property of the journal ComInG.
The originals must be accompanied by documentation of copyright transfer containing the signature of the authors.
You may not submit full or partial manuscript to another journal. The responsibility of the article's content is exclusive of the authors.
You may not translating into another language without the written permission of the Editor after consultation with the Editorial Board.
