Morad MJA, Talebiyan SR, Pakniyat E. Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications. CeN [Internet]. 2015 Dec. 19 [cited 2025 Mar. 2];37:285-90. Available from: https://periodicos.ufsm.br/cienciaenatura/article/view/20784